例句與造句

1. The thesis concludes that spectrum scan speed can reach 680mhz / s at 1khz frequency resolution when it has 8192 points complex data
   本文研究指出，譜分析數(shù)據(jù)量為8192點復(fù)數(shù)據(jù)時， 1khz頻率分辨率要求下的掃描速度可達680mhz s以上。
2. ( 3 ) design the fast calculation of modulus of 16 bit fix - point complex number and time logic of pulse compression system based on fpga ( ep1k100qc208 )
   ( 3 )基于fpga ( ep1k100qc208 )的16位定點復(fù)數(shù)的快速求模設(shè)計及系統(tǒng)時序和控制邏輯設(shè)計。
3. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future
   第五章提出了基于ieee754浮點標準的浮點運算處理器的設(shè)計和異步串行通信核的設(shè)一浙江大學(xué)博士學(xué)位論文計，提出了適合硬件實現(xiàn)的浮點乘除法、加減運算的結(jié)構(gòu)，浮點運算處理器主要用于高速fft浮點處理功能，異步串行通信核主要用于pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數(shù)據(jù)接口部分第六章提出了面向系統(tǒng)級芯片的可測試性設(shè)計包括了基于掃描測試atpg 、內(nèi)建自測試bist 、邊界掃描測試jtag設(shè)計，在討論可測試性設(shè)計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基于fpga
4. In the latter , firstly the fact that digital pulse compressing technology is one of the most important ways of signal processing in modern radar is introduced . the module of 4096 - point complex fft / ifft play a very important role in ha rdware implementation of digital pulse compressing system . secondly the basic theory of radix - 4 fft and the hardware implementation based on fpga of the 4096 - point complex fft / ifft is illustrated in detail
   在第二部分中，首先說明了數(shù)字脈壓技術(shù)是現(xiàn)代雷達中重要的信號處理技術(shù)之一，而4096點fft變換模塊就是硬件實現(xiàn)脈壓技術(shù)的核心部分，然后說明了基4fft的基本知識以及基于fpga的詳細的硬件實現(xiàn)方案。
5. The system - controlled iir filter and fft were realized using fpga in this paper , and modified pipeline structure is adopted to greatly raise the running speed in the system - controlled iir filter . in the same time , it is used that the algorithm of n - point complex to compute 2n - point real data block in the radix - 2 fft . it is different to the normal method in the adoption of pipeline single dual ram for each stage
   論文用fpga實現(xiàn)了系統(tǒng)的受控iir濾波器和fft部分，受控濾波器采用改進的流水線結(jié)構(gòu)，運行速度得到了大幅度的提高，同時運用n點復(fù)數(shù)dft算法來計算2n點實數(shù)數(shù)據(jù)，在fpga中實現(xiàn)了基2的1024點復(fù)數(shù)fft ，同一般的實現(xiàn)不同，采用了流水線式的每級單個雙口ram的方法，節(jié)省了ram的容量，經(jīng)驗證，該設(shè)計符合濾波器系統(tǒng)的要求。
6. It's difficult to find pointed complex in a sentence. 用pointed complex造句挺難的
7. In this paper what is mainly discussed is the hardware implementation of the two application specific information processing modules by cpld or fpga , which are s + p inverse transformation , the inverse transform module of an image compressing system , and 4096 - point complex fft / ifft module , the central module of the digital pulse compressing system
   本文討論的就是應(yīng)用cpld fpga來實現(xiàn)兩個專用信息處理模塊的設(shè)計。它們分別是圖象壓縮系統(tǒng)的圖象反變換模塊? s + p逆變換模塊及數(shù)字脈沖壓縮系統(tǒng)的核心模塊? 4096點fft變換模塊。